CMOS EE PLD with 192 macrocells, 12 logic elements/cells, and 5700 gates. Features a 12ns propagation delay and 100MHz maximum frequency. Operates at 3.3V with a supply voltage range of 3V to 3.6V. Offers 125 programmable I/Os and is housed in a lead-free TQFP package with tin, matte contact plating. Suitable for surface mounting, operating between 0°C and 70°C.
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Cypress CY37192VP160-100AXC technical specifications.
| Package/Case | TQFP |
| Contact Plating | Tin, Matte |
| Frequency | 100MHz |
| Lead Free | Lead Free |
| Max Frequency | 100MHz |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Max Supply Voltage | 3.6V |
| Memory Type | EEPROM, |
| Min Supply Voltage | 3V |
| Mount | Surface Mount |
| Number of Gates | 5700 |
| Number of I/Os | 125 |
| Number of Logic Blocks (LABs) | 12 |
| Number of Logic Elements/Cells | 12 |
| Number of Macro Cells | 192 |
| Number of Macrocells | 192 |
| Number of Programmable I/O | 125 |
| Operating Supply Voltage | 3.3V |
| Package Quantity | 40 |
| Packaging | Tray |
| Propagation Delay | 12ns |
| Radiation Hardening | No |
| RoHS Compliant | Yes |
| Series | Ultra37000™ |
| Speed Grade | 100 |
| Turn-On Delay Time | 12ns |
| RoHS | Compliant |
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