Synchronous SRAM chip, 18M bit density, 512K words x 36 bits, featuring a 0.45ns maximum access time and 400MHz maximum clock rate. This surface-mount component operates with a 1.8V typical supply voltage, supporting DDR data rate architecture. Encased in a 165-pin FBGA package with a 15mm x 13mm footprint and 1mm pin pitch, it offers a pipelined architecture for efficient data handling.
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Cypress CY7C11501KV18-400BZXC technical specifications.
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 165 |
| PCB | 165 |
| Package Length (mm) | 15 |
| Package Width (mm) | 13 |
| Package Height (mm) | 0.89 |
| Seated Plane Height (mm) | 1.4(Max) |
| Pin Pitch (mm) | 1 |
| Package Weight (g) | 0.49956 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 18Mbit |
| Address Bus Width | 18bit |
| Maximum Access Time | 0.45ns |
| Timing Type | Synchronous |
| Maximum Clock Rate | 400MHz |
| Data Rate Architecture | DDR |
| Density in Bits | 18874368bit |
| Maximum Operating Current | 750mA |
| Typical Operating Supply Voltage | 1.8V |
| Number of Bits per Word | 36bit |
| Number of Ports | 1 |
| Number of Words | 512K |
| Min Operating Supply Voltage | 1.7V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
| Architecture | Pipelined |
| Cage Code | 65786 |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A991.b.2.a |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
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