Synchronous SRAM chip, 36M bit density, 1M x 36 configuration, featuring a 0.45ns maximum access time and 400MHz maximum clock rate. This integrated circuit operates with a 1.8V typical supply voltage, supporting DDR data rate architecture and a pipelined design. The component is housed in a 165-pin Fine Pitch Ball Grid Array (FBGA) package, suitable for surface mounting.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Cypress CY7C1250KV18-400BZCT technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
15
Package Width (mm)
13
Package Height (mm)
0.89
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Weight (g)
0.49956
Package Material
Plastic
Mounting
Surface Mount
Density
36Mbit
Address Bus Width
19bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
400MHz
Data Rate Architecture
DDR
Density in Bits
37748736bit
Maximum Operating Current
690mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
36bit
Number of Ports
1
Number of Words
1M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Architecture
Pipelined
Compliance
Cage Code
65786
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Cypress CY7C1250KV18-400BZCT Datasheet
Download the complete datasheet for Cypress CY7C1250KV18-400BZCT to view detailed technical specifications.
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