Synchronous SRAM chip, 18M-bit density, featuring a 512K x 36 configuration. Offers a maximum access time of 6.5 ns and operates at a maximum clock rate of 133 MHz with SDR data rate architecture. This surface-mount component utilizes a 165-pin Fine Pitch Ball Grid Array (FBGA) package with a 1mm pin pitch. Designed for 3.3V operation, it supports a 19-bit address bus and has a flow-through architecture.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Cypress CY7C1371DV33-133BZI technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
15
Package Width (mm)
13
Package Height (mm)
0.89
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Weight (g)
0.49956
Package Material
Plastic
Mounting
Surface Mount
Density
18Mbit
Address Bus Width
19bit
Maximum Access Time
6.5ns
Timing Type
Synchronous
Maximum Clock Rate
133MHz
Data Rate Architecture
SDR
Density in Bits
18874368bit
Maximum Operating Current
210mA
Typical Operating Supply Voltage
3.3V
Number of Bits per Word
36bit
Number of Ports
4
Number of Words
512K
Min Operating Supply Voltage
3.135V
Max Operating Supply Voltage
3.6V
Min Operating Temperature
-40°C
Max Operating Temperature
85°C
Architecture
Flow-Through
Compliance
Cage Code
65786
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Cypress CY7C1371DV33-133BZI Datasheet
Download the complete datasheet for Cypress CY7C1371DV33-133BZI to view detailed technical specifications.
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