Synchronous SRAM chip with 18M-bit density, featuring a 1M x 18 configuration and a 20-bit address bus. Offers a maximum access time of 3 ns and a maximum clock rate of 200 MHz with SDR data rate architecture. This dual-port memory utilizes a Fine Pitch Ball Grid Array (FBGA) package, surface mountable, with 165 pins and a 1mm pin pitch. Operates at a typical supply voltage of 3.3V, with a range of 3.135V to 3.6V, and functions within an industrial temperature range of -40°C to 85°C.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Cypress CY7C1382DV33-200BZI technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
15
Package Width (mm)
13
Package Height (mm)
0.89
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Weight (g)
0.49956
Package Material
Plastic
Mounting
Surface Mount
Density
18Mbit
Address Bus Width
20bit
Maximum Access Time
3ns
Timing Type
Synchronous
Maximum Clock Rate
200MHz
Data Rate Architecture
SDR
Density in Bits
18874368bit
Maximum Operating Current
300mA
Typical Operating Supply Voltage
3.3V
Number of Bits per Word
18bit
Number of Ports
2
Number of Words
1M
Min Operating Supply Voltage
3.135V
Max Operating Supply Voltage
3.6V
Min Operating Temperature
-40°C
Max Operating Temperature
85°C
Architecture
Pipelined
Compliance
Cage Code
65786
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.b
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Cypress CY7C1382DV33-200BZI Datasheet
Download the complete datasheet for Cypress CY7C1382DV33-200BZI to view detailed technical specifications.
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