Synchronous SRAM chip, 36M-bit density, organized as 4M words x 8 bits. Features a 0.45ns maximum access time and a 300MHz maximum clock rate with QDR architecture. This surface-mount component utilizes a 165-pin Fine Pitch Ball Grid Array (FBGA) package, measuring 17mm x 15mm x 0.89mm. Operates at 1.8V typical supply voltage, with a range of 1.7V to 1.9V, and supports a 20-bit address bus.
Cypress CY7C1411JV18-300BZC technical specifications.
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