Synchronous SRAM chip, 36M-bit density, featuring a 1M x 36 configuration with a 38-bit address bus. Offers a maximum access time of 0.45 ns and a maximum clock rate of 333 MHz, utilizing a QDR data rate architecture and pipelined operation. This dual-port memory operates at 1.8V, with a voltage range of 1.7V to 1.9V, and is housed in a 165-pin FBGA surface-mount package.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Cypress CY7C1414KV18-333BZXCT technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
15
Package Width (mm)
13
Package Height (mm)
0.89
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
36Mbit
Address Bus Width
38bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
333MHz
Data Rate Architecture
QDR
Density in Bits
37748736bit
Maximum Operating Current
910mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
36bit
Number of Ports
2
Number of Words
1M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Architecture
Pipelined
Compliance
Cage Code
65786
EU RoHS
Yes
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Cypress CY7C1414KV18-333BZXCT Datasheet
Download the complete datasheet for Cypress CY7C1414KV18-333BZXCT to view detailed technical specifications.
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