Synchronous SRAM chip, 36M-bit density, featuring a 1M x 36 configuration with an 18-bit address bus. Offers a maximum access time of 0.45 ns and a maximum clock rate of 200 MHz, utilizing QDR data rate architecture. Packaged in a 165-pin Fine Pitch Ball Grid Array (FBGA) for surface mounting, operating at a typical supply voltage of 1.8V.
Cypress CY7C1415JV18-200BZXI technical specifications.
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