Synchronous SRAM chip, 36M bit density, featuring a 4M x 9-bit configuration. Delivers a maximum access time of 0.45 ns and operates at a maximum clock rate of 250 MHz with QDR architecture. This surface-mount component utilizes a 165-pin Fine Pitch Ball Grid Array (FBGA) package, measuring 17mm x 15mm x 0.89mm. Operates from a 1.8V supply voltage, with a minimum of 1.7V and a maximum of 1.9V, and supports a 20-bit address bus.
Cypress CY7C1426JV18-250BZC technical specifications.
Download the complete datasheet for Cypress CY7C1426JV18-250BZC to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.