
Synchronous SRAM chip, 144M-bit density, organized as 8M x 18 bits. Features a 0.45ns maximum access time and operates at a maximum clock rate of 333MHz with DDR data rate architecture. This surface-mount component utilizes a 165-pin Fine Pitch Ball Grid Array (FBGA) package with a 1mm pin pitch. It operates from a typical 1.8V supply voltage, with a range of 1.7V to 1.9V, and supports a 22-bit address bus.
Cypress CY7C1623KV18-333BZXC technical specifications.
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