Synchronous SRAM chip, 144M-bit density, organized as 8M x 18 bits. Features a 0.45ns maximum access time and operates at a maximum clock rate of 333MHz with DDR data rate architecture. This surface-mount component utilizes a 165-pin Fine Pitch Ball Grid Array (FBGA) package with a 1mm pin pitch. It operates from a typical 1.8V supply voltage, with a range of 1.7V to 1.9V, and supports a 22-bit address bus.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Cypress CY7C1623KV18-333BZXC technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
17
Package Width (mm)
15
Package Height (mm)
0.89
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
144Mbit
Address Bus Width
22bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
333MHz
Data Rate Architecture
DDR
Density in Bits
150994944bit
Maximum Operating Current
650mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
18bit
Number of Ports
2
Number of Words
8M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Architecture
Pipelined
Compliance
Cage Code
65786
EU RoHS
Yes
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Cypress CY7C1623KV18-333BZXC Datasheet
Download the complete datasheet for Cypress CY7C1623KV18-333BZXC to view detailed technical specifications.
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