Synchronous SRAM chip, 18M bit density, featuring a QDR data rate architecture and pipelined operation. Offers a maximum clock rate of 550 MHz with a 0.45 ns maximum access time. This dual-port memory is configured as 512K words by 36 bits, operating at 1.8 V supply voltage. Packaged in a 165-pin FBGA with a 15mm x 13mm footprint, it supports surface mounting.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Cypress CY7C2165KV18-550BZCT technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
15
Package Width (mm)
13
Package Height (mm)
0.89
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Weight (g)
0.49956
Package Material
Plastic
Mounting
Surface Mount
Density
18Mbit
Address Bus Width
17bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
550MHz
Data Rate Architecture
QDR
Density in Bits
18874368bit
Maximum Operating Current
1100mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
36bit
Number of Ports
2
Number of Words
512K
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Architecture
Pipelined
Compliance
Cage Code
65786
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Cypress CY7C2165KV18-550BZCT Datasheet
Download the complete datasheet for Cypress CY7C2165KV18-550BZCT to view detailed technical specifications.
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