Synchronous SRAM chip, 72M-bit density, featuring a 2M x 36 configuration. Operates at a maximum clock rate of 633 MHz with a 0.45 ns access time. This dual-port memory utilizes QDR architecture and a pipelined design. Packaged in a 165-pin FBGA (Fine Pitch Ball Grid Array) with a 1.0 mm pin pitch, it supports surface mounting and operates from a 1.7V to 1.9V supply, with a typical voltage of 1.8V.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Cypress CY7C2565XV18-633BZC technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
15
Package Width (mm)
13
Package Height (mm)
0.89
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Weight (g)
0.49956
Package Material
Plastic
Mounting
Surface Mount
Density
72Mbit
Address Bus Width
19bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
633MHz
Data Rate Architecture
QDR
Density in Bits
75497472bit
Maximum Operating Current
1660mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
36bit
Number of Ports
2
Number of Words
2M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Architecture
Pipelined
Compliance
Cage Code
65786
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Cypress CY7C2565XV18-633BZC Datasheet
Download the complete datasheet for Cypress CY7C2565XV18-633BZC to view detailed technical specifications.
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