Synchronous SRAM chip, 144M-bit density, featuring a 4M x 36 configuration with a 21-bit address bus. Achieves a maximum access time of 0.45 ns and a maximum clock rate of 300 MHz, utilizing QDR data rate architecture. Operates at 1.8V with a voltage range of 1.7V to 1.9V. Packaged in a 165-pin FBGA (Fine Pitch Ball Grid Array) for surface mounting, with dimensions of 17mm x 15mm x 0.89mm and a 1mm pin pitch.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Cypress CY7C2644KV18-300BZIT technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
165
PCB
165
Package Length (mm)
17
Package Width (mm)
15
Package Height (mm)
0.89
Seated Plane Height (mm)
1.4(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Density
144Mbit
Address Bus Width
21bit
Maximum Access Time
0.45ns
Timing Type
Synchronous
Maximum Clock Rate
300MHz
Data Rate Architecture
QDR
Density in Bits
150994944bit
Maximum Operating Current
1080mA
Typical Operating Supply Voltage
1.8V
Number of Bits per Word
36bit
Number of Ports
2
Number of Words
4M
Min Operating Supply Voltage
1.7V
Max Operating Supply Voltage
1.9V
Min Operating Temperature
-40°C
Max Operating Temperature
85°C
Architecture
Pipelined
Compliance
Cage Code
65786
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Cypress CY7C2644KV18-300BZIT Datasheet
Download the complete datasheet for Cypress CY7C2644KV18-300BZIT to view detailed technical specifications.
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