Low-power integrated host processor combines an e300c3 Power Architecture core with 16 Kbytes each of instruction and data cache and floating-point support. The device supports dual enhanced three-speed Ethernet controllers, dual PCI Express x1 interfaces, USB 2.0 host/device/OTG operation, PCI, TDM, SPI, I2C, DUART, DMA, and an enhanced local bus. Its memory controller supports 16-bit or 32-bit DDR1/DDR2 SDRAM at up to a 266 MHz data rate. The MPC8314E variant includes a SEC 3.3 security engine for cryptographic acceleration, and the device is offered in a 620-ball 29 mm by 29 mm Pb-free TEPBGA II package.
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| Processor core | e300c3 Power Architecture |
| Maximum core frequency | 400MHz |
| Instruction cache | 16Kbytes |
| Data cache | 16Kbytes |
| DDR memory interface width | 16 or 32bit |
| DDR data rate | 266MHz |
| Ethernet controllers | Two enhanced three-speed 10/100/1000 Mbps eTSECs |
| PCI interface | 32-bit PCI 2.3 up to 66 MHz, 3.3 V compatible |
| PCI Express interfaces | Two PCI Express 1.0a x1 interfaces |
| USB interface | USB 2.0 high-speed host/device/OTG with on-chip PHY |
| Security engine | SEC 3.3 included |
| Core supply voltage | 1.0 ± 0.05V |
| Junction temperature range | 0 to 105°C |
| Typical core power at 400 MHz | 1.167W |
| Maximum core power at 400 MHz | 1.690W |
| Package outline | 29 × 29mm |
| Interconnects | 620balls |
| Ball pitch | 1mm |
| Lead Free / Pb Free | Yes, VR package |
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