Host processor integrates an e300c3 Power Architecture core running up to 400 MHz with 16 KB instruction and 16 KB data caches. It provides dual 10/100/1000 Ethernet controllers, a 16- or 32-bit DDR1/DDR2 memory controller, dual PCI Express x1 interfaces, dual SATA 3 Gbps controllers, USB 2.0, PCI, TDM, SPI, I2C, DUART, local bus, DMA, timers, and GPIO. The non-encryption version does not include the security engine available on E-suffix devices. It operates from 1.0 V core supplies with 1.8 V or 2.5 V DDR I/O options and is specified for 0 to 105 °C or -40 to 105 °C orderable temperature ranges. The device is supplied in a 620-ball, 29 mm by 29 mm Pb-free TEPBGA II package.
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| Processor core | e300c3 Power Architecture |
| Maximum core frequency | 400MHz |
| Instruction cache | 16KB |
| Data cache | 16KB |
| DDR memory interface width | 16 or 32bit |
| DDR memory data rate | up to 266MHz |
| Ethernet controllers | Dual enhanced 10/100/1000 Mbps eTSEC |
| Ethernet interfaces | RGMII, MII, RMII, RTBI, or SGMII |
| PCI interface | 32-bit PCI 2.3 up to 66 MHz, 3.3 V |
| PCI Express interfaces | Dual x1 PCI Express 1.0a |
| SATA controllers | Dual SATA 1.5 and 3.0 Gbps |
| USB interface | USB 2.0 host, device, or OTG with on-chip PHY |
| Local bus | 16-bit enhanced local bus up to 66 MHz |
| TDM time slots | Up to 128 |
| Core supply voltage | 1.0 ± 0.05V |
| DDR I/O voltage | 1.8 ± 0.1 or 2.5 ± 0.2V |
| Typical core power at 400 MHz | 1.167W |
| Maximum core power at 400 MHz | 1.690W |
| Package interconnects | 620 solder balls |
| Package pitch | 1mm |
| Lead Free | Pb-free TEPBGA II package |
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