Synchronous SRAM chip with 144M-bit density, organized as 8M x 18 bits, featuring dual 1.8V/2.5V operating supply voltages and a maximum clock rate of 200 MHz. This surface-mount component utilizes a Fine Pitch Ball Grid Array (FBGA) package with 119 pins and a 1.27mm pin pitch. It offers maximum access times of 7.5ns (Flow-Through) and 3ns (Pipelined), with an 18-bit data bus and 23-bit address bus. Operating across a temperature range of -40°C to 85°C, this memory IC supports both Flow-Through and Pipelined architectures.
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| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 119 |
| PCB | 119 |
| Package Length (mm) | 22 |
| Package Width (mm) | 14 |
| Package Height (mm) | 1.26 |
| Seated Plane Height (mm) | 1.86 |
| Pin Pitch (mm) | 1.27 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 144Mbit |
| Address Bus Width | 23bit |
| Maximum Access Time | 7.5@Flow-Through|3@Pipelinedns |
| Timing Type | Synchronous |
| Maximum Clock Rate | 200MHz |
| Data Rate Architecture | SDR |
| Density in Bits | 150994944bit |
| Maximum Operating Current | 360@Flow-Through|435@PipelinedmA |
| Typical Operating Supply Voltage | 1.8|2.5V |
| Number of Bits per Word | 18bit |
| Number of Ports | 2 |
| Number of Words | 8M |
| Min Operating Supply Voltage | 1.7|2.3V |
| Max Operating Supply Voltage | 2|2.7V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
| Architecture | Flow-Through|Pipelined |
| Cage Code | 3BKC7 |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A991.b.2.b |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
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