The HD74LS374, 8-bit registers features totem-pole three-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide this register with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for inter-face or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops are edge-triggered D-type flip-flops. On the positive transition the clock, the Q outputs will be set to the logic states that were setup at the D inputs.
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| Supply voltage (Vcc) min | 4.75V |
| Supply voltage (Vcc) typ | 5.00V |
| Supply voltage (Vcc) max | 5.25V |
| Output voltage (VOH) | 5.5V |
| Output current (IOH) | -2.6mA |
| Output current (IOL) | 24mA |
| Clock pulse width ("H" level, tw) | 15ns |
| Clock pulse width ("L" level, tw) | 15ns |
| Data setup time (tsu) | 20ns |
| Data hold time (th) | 31ns |
| Input voltage (VIH) min | 2.0V |
| Input voltage (VIL) max | 0.8V |
| Output voltage (VOH) min (Vcc=4.75V, VIH=2V, VIL=0.8V, IOH=-2.6mA) | 2.4V |
| Output voltage (VOL) max (Vcc=4.75V, VIH=2V, IOL=12mA) | 0.4V |
| Output voltage (VOL) max (Vcc=4.75V, VIL=0.8V, IOL=24mA) | 0.5V |
| Off-state output current (IOZH) max (Vcc=5.25V, VIH=2V, Vo=2.7V) | 20μA |
| Off-state output current (IOZL) min (Vcc=5.25V, VIL=0.8V, Vo=0.4V) | -20μA |
| Input current (IIH) max (Vcc=5.25V, VI=2.7V) | 20μA |
| Input current (IIL) max (Vcc=5.25V, VI=0.4V) | -0.4mA |
| Input current (II) max (Vcc=5.25V, VI=7V) | 0.1mA |
| Short-circuit output current (IOS) min (Vcc=5.25V) | 30mA |
| Short-circuit output current (IOS) max (Vcc=5.25V) | -130mA |
| Supply current (ICC) typ (Vcc=5.25V, VI=4.5V (Output control)) | 27mA |
| Supply current (ICC) max (Vcc=5.25V, VI=4.5V (Output control)) | 40mA |
| Input clamp voltage (VIK) max (Vcc=4.75V, IIN=-18mA) | -1.5V |
| Maximum clock frequency (fmax) min | 35MHz |
| Maximum clock frequency (fmax) typ | 50MHz |
| Propagation delay time (tPLH) max (Clock to Q, CL=45pF, RL=667Ω) | 28ns |
| Propagation delay time (tPHL) max (Clock to Q, CL=45pF, RL=667Ω) | 28ns |
| Output enable time (tPZL) max (OC to Q, CL=45pF, RL=667Ω) | 28ns |
| Output enable time (tPZH) max (OC to Q, CL=45pF, RL=667Ω) | 28ns |
| Output disable time (tPLZ) max (OC to Q, CL=5pF, RL=667Ω) | 20ns |
| Output disable time (tPHZ) max (OC to Q, CL=5pF, RL=667Ω) | 25ns |
| RoHS | Not Compliant |
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