Dual J-K Flip-Flop, LVC/LCX/Z family, featuring complementary outputs and negative edge triggering. Operates with a nominal supply voltage of 3.3V, ranging from 2.7V to 3.6V. Offers a propagation delay of 7.1ns, with a typical 5.9ns at nominal supply. This 2-bit logic IC supports industrial temperature grades from -40°C to 85°C and comes in a 16-terminal PDSO package.
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Technical Specifications
Integrated Device Technology IDT74LVC112APY technical specifications.
General
| Max Operating Temperature | 85 |
| Number of Terminals | 16 |
| Min Operating Temperature | -40 |
| Terminal Position | DUAL |
| JEDEC Package Code | R-PDSO-G16 |
| Width | 5.3 |
| Length | 6.2 |
| Pin Count | 16 |
| Number of Functions | 2 |
| Temperature Grade | INDUSTRIAL |
| Supply Voltage-Nom (Vsup) | 3.3 |
| Supply Voltage-Max (Vsup) | 3.6 |
| Supply Voltage-Min (Vsup) | 2.7 |
| Logic IC Type | J-K FLIP-FLOP |
| Family | LVC/LCX/Z |
| Propagation Delay (tpd) | 7.1 |
| Number of Bits | 2 |
| Max I(ol) | 0.024 |
| Prop. Delay@Nom-Sup | 5.9 |
| Load Capacitance | 50 |
| Output Polarity | COMPLEMENTARY |
| Trigger Type | NEGATIVE EDGE |
| fmax-Min | 150 |
| Max Frequency@Nom-Sup | 150000000 |
Compliance
| RoHS | No |
| HTS Code | 8542.39.00.01 |
| REACH | not_compliant |
| Military Spec | False |
Datasheet
Integrated Device Technology IDT74LVC112APY Datasheet
Download the complete datasheet for Integrated Device Technology IDT74LVC112APY to view detailed technical specifications.
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