Synchronous SRAM chip, 2M-bit density, featuring a 64K x 32 configuration. This integrated circuit offers a maximum access time of 7 ns and a maximum clock rate of 66 MHz with SDR data rate architecture. Packaged in a 100-pin LQFP (Low Profile Quad Flat Package) with gull-wing leads for surface mounting, it operates at a typical 3.3V supply voltage. The component is constructed from plastic and designed for a pipelined architecture.
Kioxia TC55V2325FF-7(G,IN technical specifications.
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | QFP |
| Package/Case | LQFP |
| Package Description | Low Profile Quad Flat Package |
| Lead Shape | Gull-wing |
| Pin Count | 100 |
| PCB | 100 |
| Package Length (mm) | 20 |
| Package Width (mm) | 14 |
| Package Height (mm) | 1.4 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 2Mbit |
| Address Bus Width | 16bit |
| Maximum Access Time | 7ns |
| Timing Type | Synchronous |
| Maximum Clock Rate | 66MHz |
| Data Rate Architecture | SDR |
| Density in Bits | 2097152bit |
| Maximum Operating Current | 200mA |
| Typical Operating Supply Voltage | 3.3V |
| Number of Bits per Word | 32bit |
| Number of Ports | 1 |
| Number of Words | 64K |
| Min Operating Supply Voltage | 3.1V |
| Max Operating Supply Voltage | 3.6V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
| Architecture | Pipelined |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A991.b.2.a |
| RoHS Versions | 2011/65/EU |
No datasheet is available for this part.
