Complex Programmable Logic Device (CPLD) featuring 8,000 gates and 192 macrocells. Offers 96 programmable I/Os and operates at a maximum frequency of 100MHz, with a typical propagation delay of 12.5ns. Designed for surface mounting in a 128-pin PQFP package, this EEPROM-based device supports a 5V operating supply voltage (4.75V to 5.25V) and operates within a temperature range of 0°C to 70°C. RoHS compliant.
Lattice Semiconductor ISPLSI1048E-100LQN technical specifications.
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