128 Macro Cell Complex Programmable Logic Device (CPLD) featuring 64 I/Os and 8 Logic Blocks. Operates at a maximum frequency of 200MHz with a typical propagation delay of 5.8ns and turn-on delay of 7.5ns. This surface mount device utilizes EEPROM memory and is housed in a 100-pin TQFP package. It supports an operating supply voltage of 1.8V, ranging from 1.7V to 1.9V, and is RoHS compliant.
Lattice Semiconductor LC4128ZE-7TN100C technical specifications.
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