CMOS EE PLD with 5ns propagation delay, featuring 256-cell architecture and 1140 macrocells. Operates at a maximum frequency of 322MHz, with a typical operating frequency of 227.27MHz. This surface mount device supports 271 I/Os, including 160 programmable I/Os, and requires a 3V to 3.6V supply voltage, with a standard operating voltage of 3.3V. It offers 16 logic blocks (LABs) and 36 logic elements/cells, packaged in an LBGA (FTBGA-256) format. RoHS compliant and lead-free.
Lattice Semiconductor LC4256V-5FTN256BC technical specifications.
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