Complex Programmable Logic Device (CPLD) featuring 768 macrocells and 225K gates, operating at a maximum frequency of 250MHz. This surface-mount device utilizes an FBGA package and supports a supply voltage range of 2.3V to 2.7V, with a nominal 2.5V. It offers 193 I/Os, including 176 programmable I/Os, and boasts a propagation delay of 5ns. The CPLD is designed for operation between 0°C and 90°C and includes 393216 bits of RAM.
Lattice Semiconductor LC5768MB-5F256C technical specifications.
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