This Complex Programmable Logic Device (CPLD) offers 32 macro cells and 1.25K gates, operating at 182MHz with a 5V supply. Featuring 32 user I/Os and 16 product terms per macro, this ROMLess CPLD supports in-system programmability. Packaged in a 44-pin PLCC (Plastic Leaded Chip Carrier) with J-lead configuration, it is designed for surface mounting. The device operates within a temperature range of 0°C to 70°C.
PackagePLCC
MountingSurface Mount
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Technical Specifications
Lattice Semiconductor MACH111-5JC technical specifications.
General
Basic Package Type
Lead-Frame SMT
Package Family Name
LCC
Package/Case
PLCC
Package Description
Plastic Leaded Chip Carrier
Lead Shape
J-Lead
Pin Count
44
PCB
44
Package Length (mm)
16.59
Package Width (mm)
16.59
Package Height (mm)
3.68(Min)
Pin Pitch (mm)
1.27
Package Material
Plastic
Mounting
Surface Mount
Jedec
MS-018AC
Family Name
MACH 1
Number of User I/Os
32
Number of Product Terms per Macro
16
Number of Logic Blocks/Elements
2
Number of Macro Cells
32
Program Memory Type
ROMLess
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Typical Operating Supply Voltage
5V
Min Operating Supply Voltage
4.75V
Programmability
Yes
In-System Programmability
Yes
Speed Grade
5
Compliance
Cage Code
66675
EU RoHS
No
HTS Code
8542390001
Schedule B
8542390000
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Lattice Semiconductor MACH111-5JC Datasheet
Download the complete datasheet for Lattice Semiconductor MACH111-5JC to view detailed technical specifications.
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