Asynchronous SRAM chip, 64K-bit density (8K x 8 words), featuring a 40ns maximum access time. This 28-pin Side Brazed Ceramic Dual In Line Package (SBCDIP) component operates with a typical supply voltage of 5V (4.5V to 5.5V range) and supports through-hole mounting. It offers a 13-bit address bus and a maximum operating current of 80mA, suitable for applications requiring reliable memory storage across a wide temperature range of -55°C to 125°C.
PackageSBCDIP
MountingThrough Hole
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Technical Specifications
Microchip AT65609EHW-CI40MQ technical specifications.
General
| Basic Package Type | Through Hole |
| Package Family Name | DIP |
| Package/Case | SBCDIP |
| Package Description | Side Brazed Ceramic Dual In Line Package |
| Lead Shape | Through Hole |
| Pin Count | 28 |
| PCB | 28 |
| Package Length (mm) | 35.56 |
| Package Width (mm) | 15.11 |
| Package Height (mm) | 2.73 |
| Package Material | Ceramic |
| Mounting | Through Hole |
| Density | 64Kbit |
| Address Bus Width | 13bit |
| Maximum Access Time | 40ns |
| Timing Type | Asynchronous |
| Density in Bits | 65536bit |
| Maximum Operating Current | 80mA |
| Typical Operating Supply Voltage | 5V |
| Number of Bits per Word | 8bit |
| Number of Ports | 1 |
| Number of Words | 8K |
| Min Operating Supply Voltage | 4.5V |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | -55°C |
| Max Operating Temperature | 125°C |
Compliance
| Cage Code | 60991 |
| EU RoHS | No |
| HTS Code | 8542320071 |
| Schedule B | 8542320040 |
| ECCN | 3A001.a.2.c |
| Radiation Hardening | Yes |
| Dose Level | 300 |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Microchip AT65609EHW-CI40MQ Datasheet
Download the complete datasheet for Microchip AT65609EHW-CI40MQ to view detailed technical specifications.
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