8-bit CISC microcontroller featuring an 8051 core, 20 MHz clock speed, and 24KB Flash program memory. This surface-mount device offers 1.375KB RAM, 40 programmable I/Os, and three timers. It supports SPI and UART interfaces and operates from 3.3V to 5.5V. Packaged in a 44-pin TQFP with a 0.8mm pin pitch, it is suitable for a wide temperature range of -40°C to 85°C. Includes 8 ADC channels.
PackageTQFP
MountingSurface Mount
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Technical Specifications
Microchip AT89LP51RB2-20AUR technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | QFP |
| Package/Case | TQFP |
| Package Description | Thin Quad Flat Package |
| Lead Shape | Gull-wing |
| Pin Count | 44 |
| PCB | 44 |
| Package Length (mm) | 10.1(Max) |
| Package Width (mm) | 10.1(Max) |
| Package Height (mm) | 1.05(Max) |
| Seated Plane Height (mm) | 1.2(Max) |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-026ACB |
| Family Name | AT89 |
| Data Bus Width | 8bit |
| Instruction Set Architecture | CISC |
| Maximum Clock Rate | 20MHz |
| Maximum CPU Frequency | 20MHz |
| Device Core | 8051 |
| Program Memory Type | Flash |
| Program Memory Size | 24KB |
| RAM Size | 1.375KB |
| Number of Programmable I/Os | 40 |
| Core Architecture | 8051 |
| Programmability | Yes |
| Number of Timers | 3 |
| Interface Type | SPI/UART |
| CAN | 0 |
| I2C | 0 |
| SPI | 1 |
| Ethernet | 0 |
| UART | 1 |
| USART | 0 |
| USB | 0 |
| I2S | 0 |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
| ADC Channels | 8 |
| Number of ADCs | Single |
Compliance
| Cage Code | 60991 |
| EU RoHS | Yes |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Microchip AT89LP51RB2-20AUR Datasheet
Download the complete datasheet for Microchip AT89LP51RB2-20AUR to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.