
16/32-bit ARM7TDMI RISC microcontroller featuring a 55 MHz maximum clock rate and 128KB Flash program memory. This MCU offers 32KB RAM, 62 programmable I/Os, and integrated peripherals including CAN, Ethernet, SPI, USART, and USB interfaces. Packaged in a 100-pin LQFP (Low Profile Quad Flat Package) with a 0.5mm pin pitch, it supports surface mounting and operates from 1.8V with a temperature range of -40°C to 85°C. Additional features include 8 ADC channels.
Microchip AT91SAM7XC128B-AU-999 technical specifications.
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | QFP |
| Package/Case | LQFP |
| Package Description | Low Profile Quad Flat Package |
| Lead Shape | Gull-wing |
| Pin Count | 100 |
| PCB | 100 |
| Package Length (mm) | 14 |
| Package Width (mm) | 14 |
| Package Height (mm) | 1.4 |
| Seated Plane Height (mm) | 1.6(Max) |
| Pin Pitch (mm) | 0.5 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-026BED |
| Family Name | AT91 |
| Data Bus Width | 16|32bit |
| Instruction Set Architecture | RISC |
| Maximum Clock Rate | 55MHz |
| Maximum CPU Frequency | 55MHz |
| Device Core | ARM7TDMI |
| Program Memory Type | Flash |
| Program Memory Size | 128KB |
| RAM Size | 32KB |
| Number of Programmable I/Os | 62 |
| Core Architecture | ARM |
| Programmability | Yes |
| Number of Timers | 3 |
| Interface Type | CAN/Ethernet/SPI/TWI/USART/USB |
| CAN | 1 |
| I2C | 0 |
| SPI | 2 |
| Ethernet | 1 |
| UART | 0 |
| USART | 2 |
| USB | 1 |
| I2S | 0 |
| Max Operating Supply Voltage | 1.95V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
| ADC Channels | 8 |
| Number of ADCs | Single |
| Cage Code | 60991 |
| EU RoHS | Yes |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Download the complete datasheet for Microchip AT91SAM7XC128B-AU-999 to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.