DDR2 SDRAM memory chip, 1Gbit density, organized as 256Mx4 with a 4-bit data bus width. Features an 800 MHz maximum clock rate and 8 internal banks. Housed in a 60-pin FBGA package with 0.8mm pin pitch, designed for surface mounting. Operates at a typical 1.8V supply voltage, with a maximum access time of 0.4 ns.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Micron MT47H256M4CF-25E:H technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
60
PCB
60
Package Length (mm)
10
Package Width (mm)
8
Package Height (mm)
0.8
Seated Plane Height (mm)
1.2(Max)
Pin Pitch (mm)
0.8
Package Material
Plastic
Mounting
Surface Mount
Density
1Gbit
Type
DDR2 SDRAM
Organization
256Mx4
Data Bus Width
4bit
Maximum Clock Rate
800MHz
Number of Internal Banks
8
Number of Words per Bank
32M
Maximum Access Time
0.4ns
Density in Bits
1073741824bit
Address Bus Width
17bit
Maximum Operating Current
125mA
Typical Operating Supply Voltage
1.8V
Max Operating Supply Voltage
1.9V
Min Operating Supply Voltage
1.7V
Min Operating Temperature
0°C
Max Operating Temperature
85°C
Compliance
Cage Code
6Y440
EU RoHS
Yes
HTS Code
8542320032
Schedule B
8542320015
ECCN
EAR99
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Micron MT47H256M4CF-25E:H Datasheet
Download the complete datasheet for Micron MT47H256M4CF-25E:H to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.