DDR2 SDRAM memory chip offering 2Gbit density with a 256Mx8 organization and 8-bit data bus width. Features a 60-pin FBGA package with a 0.8mm pin pitch, designed for surface mount applications. Operates at a maximum clock rate of 667 MHz with a typical supply voltage of 1.8V. This component supports 8 internal banks and has a maximum access time of 0.45 ns, suitable for a wide operating temperature range of -40°C to 85°C.
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| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 60 |
| PCB | 60 |
| Package Length (mm) | 14 |
| Package Width (mm) | 11.5 |
| Package Height (mm) | 1.2(Max) - 0.25(Min) |
| Seated Plane Height (mm) | 1.2(Max) |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 2Gbit |
| Type | DDR2 SDRAM |
| Organization | 256Mx8 |
| Data Bus Width | 8bit |
| Maximum Clock Rate | 667MHz |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 32M |
| Maximum Access Time | 0.45ns |
| Density in Bits | 2147483648bit |
| Address Bus Width | 18bit |
| Maximum Operating Current | 170mA |
| Typical Operating Supply Voltage | 1.8V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Supply Voltage | 1.7V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
| Cage Code | 6Y440 |
| HTS Code | 8542320036 |
| Schedule B | 8542320023 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
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