A 32-bit integrated processor combines a CPU32 M68000-compatible core with DMA, serial, timer, system-integration, and external bus functions on one device. The exact orderable version operates from a 5.0 V supply at 0 MHz to 16.78 MHz over a 0°C to 70°C temperature range. It uses an FE-suffix 144-pin ceramic quad flat pack package. On-chip peripherals include a two-channel DMA controller, two-channel USART, two independent 16-bit counter/timers, programmable chip selects, bus arbitration, system protection, and IEEE 1149.1 boundary scan support.
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| Processor architecture | CPU32, M68000-compatible 32-bit CISC |
| Supply voltage | 5.0V |
| Operating frequency | 0 to 16.78MHz |
| Operating temperature | 0 to +70°C |
| Package pins | 144pins |
| Package type | Ceramic Quad Flat Pack (CQFP) |
| Address bus width | 32bit |
| Data bus width | 16bit |
| DMA channels | 2 |
| DMA transfer widths | 8, 16, 32bit |
| DMA sustained transfer rate | 50Mbyte/s |
| USART channels | 2 |
| USART maximum transfer rate | 9.8Mbit/s |
| Counter/timers | 2 independent 16-bit |
| Timer prescaler | Up to 8bit |
| Timer resolution | 80ns |
| Boundary scan | IEEE 1149.1 JTAG |
| Thermal resistance junction-to-ambient | 33, ceramic 144-pin QFP°C/W |
| Power dissipation | 945 at 5 V, 16.78 MHzmW |
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Technical updates and corrections for the MC68340 processor, covering timing diagrams, pin assignments, package dimensions, and ordering information for 5.0V and 3.3V variants.
