The integrated processor combines a CPU32 core, two-channel DMA controller, serial I/O, timers, chip selects, and system integration logic on one device. It supports an M68000-compatible 32-bit CISC programming model with a 16-bit external data bus and operation up to 16.78 MHz for the FE16 ordering variant. The FE suffix package is a 144-lead ceramic quad flat pack with 0.65 mm lead spacing for surface-mount assembly. The 5 V device supports 0 °C to 70 °C operation in the standard FE16 ordering table and includes IEEE 1149.1 boundary-scan test support.
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| Core | CPU32, M68000-compatible |
| Maximum operating frequency | 16.78MHz |
| Supply voltage | 5.0 ±5%V |
| Package | 144-lead ceramic quad flat pack |
| Package suffix | FE |
| Operating temperature | 0 to 70°C |
| External data bus width | 16bit |
| DMA channels | 2 |
| DMA transfer width | 8, 16, or 32bit |
| DMA sustained transfer rate | 33.3 single-address, 8.4 dual-address at 16.78 MHzMbyte/s |
| Serial channels | 2 |
| Serial maximum transfer rate | 6.5 in 1x mode at 16.78 MHzMbit/s |
| Timer modules | 2 |
| Timer resolution | 125 at 16.78 MHzns |
| Boundary scan | IEEE 1149.1 JTAG |
| Typical power consumption | 500 full operation at 16.78 MHzmW |
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These are design resources that include the Motorola MC68340FE16C
Technical addendum for the MC68340 processor covering CPU32 operand alignment, interrupt latency, bus arbitration priority, and PLL clock configuration updates.
