The integrated processor combines a CPU32 M68000-compatible 32-bit CISC core with direct memory access and on-chip peripheral subsystems. It operates at up to 25 MHz and delivers 4.8 MIPS at 25 MHz. The device includes a two-channel DMA controller, two-channel serial I/O, two independent 16-bit counter/timers, a system integration module, and IEEE 1149.1 boundary-scan support. The LQFP package has 144 leads with a 20 mm by 20 mm body, 1.4 mm height, and 0.5 mm pitch.
Checking distributor stock and pricing after the page loads.
Sign in to ask questions about the Motorola MC68340PV25 datasheet using AI. Get instant answers about specifications, features, and technical details, ideal for finding information in larger documents.
Sign In to ChatWidest selection of semiconductors and electronic components in stock and ready to ship ™
| Processor core | CPU32 |
| Architecture | 32-bit CISC, M68000-compatible |
| Maximum clock frequency | 25MHz |
| Performance | 4.8 at 25 MHzMIPS |
| Address lines | 32 |
| Data bus width | 16bit |
| DMA controller | Two-channel low-latency DMA |
| DMA transfer width | 8, 16, and 32bit |
| Sustained DMA transfer rate | 50Mbyte/s |
| Memory-to-memory DMA transfer rate | 12.5Mbyte/s |
| Serial channels | Two-channel USART |
| Maximum serial transfer rate | 9.8Mbit/s |
| Timers | Two independent 16-bit counter/timers |
| Timer resolution | 80ns |
| Boundary scan | IEEE 1149.1 JTAG |
| Package | 144-LQFP |
Download the complete datasheet for Motorola MC68340PV25 to view detailed technical specifications.
The embedded preview will load automatically when this section scrolls into view.
These are design resources that include the Motorola MC68340PV25
Technical updates and corrections for the MC68340 processor, covering timing diagrams, pin assignments, package dimensions, and ordering information for 5.0V and 3.3V variants.
