Integrated messaging processor combines a 32-bit MCORE RISC CPU with a Roaming FLEX alphanumeric paging decoder. The device supports FLEX decoding at 1600, 3200, and 6400 bps with programmable receiver control, SSID and NID roaming, message fragmentation, and group messaging. On-chip resources include 96 KB of ROM, 6 KB of RAM, SCI with IrDA capability, SPI, a frequency synthesizer controller, a melody generator, keypad interface, timers, and multipurpose I/O. Operation is specified over a 1.8 V to 3.6 V supply range and a -20 °C to 85 °C temperature range, with processor operation up to 10 MHz.
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| Processor architecture | 32-bit MCORE RISC |
| Instruction length | 16bit |
| General-purpose registers | 16 x 32-bit |
| Maximum processor frequency | 10MHz |
| Supply voltage range | 1.8 to 3.6V |
| Operating temperature range | -20 to 85°C |
| On-chip ROM | 96KB |
| On-chip RAM | 6KB |
| FLEX decoder data rates | 1600, 3200, 6400bps |
| External system bus width | 8 or 16bit |
| External address bus width | 22bit |
| Chip-select outputs | 4 external devices |
| Addressable memory per chip select | 4MB |
| Directly addressable memory | 16MB |
| General-purpose timers | Two 16-bit timers |
| Keypad interface | 4 x 4 |
| BGA package size | 12 x 12mm |
| BGA ball pitch | 0.8mm |
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