The digital signal controller combines a 56800E DSP core with microcontroller peripherals for control applications. It operates at up to 60 MHz and integrates 64 KB of flash memory with 8 KB of unified RAM. The device includes eFlexPWM with six high-resolution NanoEdge PWM outputs, dual 12-bit ADCs with programmable gain, three analog comparators, QSPI, dual QSCI, dual I2C/SMBus interfaces, MSCAN, timers, CRC, watchdog, PLL, and JTAG/EOnCE debug. It operates from a single 3.0 V to 3.6 V supply and is implemented in a 64-pin LQFP package. Temperature-suffix variants support either -40 °C to +105 °C or -40 °C to +125 °C operation, and the family is not recommended for new designs.
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| Core architecture | 56800E digital signal processor core |
| Maximum operating frequency | 60MHz |
| Performance | 60MIPS |
| Flash memory | 64KB |
| RAM | 8KB |
| Supply voltage | 3.0 to 3.6V |
| Package | 64-pin LQFP |
| GPIO | 54pins |
| High-resolution PWM outputs | 6channels |
| PWM resolution | 520ps |
| ADC | Two 8-channel 12-bit ADCs with x1, x2, x4 programmable gain |
| ADC conversion time | 600 minimumns |
| Analog comparators | 3 with integrated 5-bit DAC referenceschannels |
| QSPI interfaces | 1interfaces |
| QSCI interfaces | 2 with LIN slave functionalityinterfaces |
| I2C/SMBus interfaces | 2interfaces |
| CAN interface | MSCAN 2.0 A/B |
| Timers | Two 16-bit quad timers |
| Operating temperature, V suffix | -40 to +105°C |
| Operating temperature, M suffix | -40 to +125°C |
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