Asynchronous SRAM chip, 72K-bit density, organized as 8K words by 9 bits. Features a 25ns maximum access time and operates from a 4.5V to 5.5V supply, with a typical 5V requirement. This 28-pin component utilizes a Side Brazed Ceramic Dual In Line Package (SBCDIP) with through-hole mounting and a 2.54mm pin pitch. Designed for operation across a wide temperature range of -55°C to 125°C.
PackageSBCDIP
MountingThrough Hole
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Technical Specifications
Pyramid P4C163-25CMBLF technical specifications.
General
Basic Package Type
Through Hole
Package Family Name
DIP
Package/Case
SBCDIP
Package Description
Side Brazed Ceramic Dual In Line Package
Lead Shape
Through Hole
Pin Count
28
PCB
28
Package Length (mm)
37.72(Max)
Package Width (mm)
7.87(Max)
Package Height (mm)
3.94(Max)
Seated Plane Height (mm)
5.72(Max)
Pin Pitch (mm)
2.54
Package Material
Ceramic
Mounting
Through Hole
Density
72Kbit
Address Bus Width
13bit
Maximum Access Time
25ns
Timing Type
Asynchronous
Density in Bits
73728bit
Maximum Operating Current
145mA
Typical Operating Supply Voltage
5V
Number of Bits per Word
9bit
Number of Ports
1
Number of Words
8K
Min Operating Supply Voltage
4.5V
Max Operating Supply Voltage
5.5V
Min Operating Temperature
-55°C
Max Operating Temperature
125°C
Compliance
Cage Code
3DTT2
EU RoHS
Yes
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A001.a.2.c
Automotive
No
AEC Qualified
No
PPAP
No
RoHS Versions
2002/95/EC
Datasheet
Pyramid P4C163-25CMBLF Datasheet
Download the complete datasheet for Pyramid P4C163-25CMBLF to view detailed technical specifications.
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