Asynchronous SRAM chip, 72K bit density, organized as 8K words by 9 bits. Features a 35ns maximum access time and operates from a 5V supply. This component is housed in a 28-pin Side Brazed Ceramic Dual In Line Package (SBCDIP) with through-hole mounting. Designed for a wide operating temperature range of -55°C to 125°C.
PackageSBCDIP
MountingThrough Hole
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Technical Specifications
Pyramid P4C163-35CMLF technical specifications.
General
| Basic Package Type | Through Hole |
| Package Family Name | DIP |
| Package/Case | SBCDIP |
| Package Description | Side Brazed Ceramic Dual In Line Package |
| Lead Shape | Through Hole |
| Pin Count | 28 |
| PCB | 28 |
| Package Length (mm) | 37.72(Max) |
| Package Width (mm) | 7.87(Max) |
| Package Height (mm) | 3.94(Max) |
| Seated Plane Height (mm) | 5.72(Max) |
| Pin Pitch (mm) | 2.54 |
| Package Material | Ceramic |
| Mounting | Through Hole |
| Density | 72Kbit |
| Address Bus Width | 13bit |
| Maximum Access Time | 35ns |
| Timing Type | Asynchronous |
| Density in Bits | 73728bit |
| Maximum Operating Current | 120mA |
| Typical Operating Supply Voltage | 5V |
| Number of Bits per Word | 9bit |
| Number of Ports | 1 |
| Number of Words | 8K |
| Min Operating Supply Voltage | 4.5V |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | -55°C |
| Max Operating Temperature | 125°C |
Compliance
| Cage Code | 3DTT2 |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A001.a.2.c |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Pyramid P4C163-35CMLF Datasheet
Download the complete datasheet for Pyramid P4C163-35CMLF to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.