Asynchronous SRAM chip, 64K-bit density, organized as 8K words by 8 bits. Features a maximum access time of 35 ns and operates from a 4.5V to 5.5V supply, with a typical 5V requirement. This 28-pin Ceramic Dual In-line Package (CDIP) component is designed for through-hole mounting and offers a 13-bit address bus. Operating temperature range is -55°C to 125°C.
PackageCDIP
MountingThrough Hole
Quick Jump:
Technical Specifications
Pyramid P4C164-35DMBLF technical specifications.
General
| Basic Package Type | Through Hole |
| Package Family Name | DIP |
| Package/Case | CDIP |
| Package Description | Ceramic Dual In Line Package |
| Lead Shape | Through Hole |
| Pin Count | 28 |
| PCB | 28 |
| Package Length (mm) | 37.72(Max) |
| Package Width (mm) | 7.87(Max) |
| Package Height (mm) | 4.19(Max) |
| Seated Plane Height (mm) | 5.72(Max) |
| Pin Pitch (mm) | 2.54 |
| Package Material | Ceramic |
| Mounting | Through Hole |
| Density | 64Kbit |
| Address Bus Width | 13bit |
| Maximum Access Time | 35ns |
| Timing Type | Asynchronous |
| Density in Bits | 65536bit |
| Maximum Operating Current | 150mA |
| Typical Operating Supply Voltage | 5V |
| Number of Bits per Word | 8bit |
| Number of Ports | 1 |
| Number of Words | 8K |
| Min Operating Supply Voltage | 4.5V |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | -55°C |
| Max Operating Temperature | 125°C |
Compliance
| Cage Code | 3DTT2 |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A001.a.2.c |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Pyramid P4C164-35DMBLF Datasheet
Download the complete datasheet for Pyramid P4C164-35DMBLF to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.