Asynchronous SRAM chip, 128K bit density, 8K x 16 configuration, featuring 20ns maximum access time. This dual-port memory operates with a typical 5V supply voltage, ranging from 4.5V to 5.5V. The component is housed in an 84-pin PLCC (Plastic Leaded Chip Carrier) package with J-lead surface mount technology, conforming to Jedec MS-018AF. It supports a 26-bit address bus and operates within a temperature range of -55°C to 125°C.
PackagePLCC
MountingSurface Mount
Quick Jump:
Technical Specifications
Renesas 7025L20JGB8 technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | LCC |
| Package/Case | PLCC |
| Package Description | Plastic Leaded Chip Carrier |
| Lead Shape | J-Lead |
| Pin Count | 84 |
| PCB | 84 |
| Package Length (mm) | 29.31 |
| Package Width (mm) | 29.31 |
| Package Height (mm) | 3.68(Min) |
| Seated Plane Height (mm) | 4.37 |
| Pin Pitch (mm) | 1.27 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-018AF |
| Density | 128Kbit |
| Address Bus Width | 26bit |
| Maximum Access Time | 20ns |
| Timing Type | Asynchronous |
| Data Rate Architecture | SDR |
| Density in Bits | 131072bit |
| Maximum Operating Current | 320mA |
| Typical Operating Supply Voltage | 5V |
| Number of Bits per Word | 16bit |
| Number of Ports | 2 |
| Number of Words | 8K |
| Min Operating Supply Voltage | 4.5V |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | -55°C |
| Max Operating Temperature | 125°C |
Compliance
| Cage Code | SAN34 |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A001.a.2.c |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Renesas 7025L20JGB8 Datasheet
Download the complete datasheet for Renesas 7025L20JGB8 to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.