128K-bit asynchronous SRAM chip featuring an 8K x 16 configuration. This surface-mount component offers a maximum access time of 55 ns and operates with a typical supply voltage of 5V. The 84-pin PLCC package utilizes J-lead technology for secure mounting. Designed for a wide temperature range from -55°C to 125°C, this dual-port memory provides 131072 bits of storage.
PackagePLCC
MountingSurface Mount
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Technical Specifications
Renesas 7025L55JGB8 technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | LCC |
| Package/Case | PLCC |
| Package Description | Plastic Leaded Chip Carrier |
| Lead Shape | J-Lead |
| Pin Count | 84 |
| PCB | 84 |
| Package Length (mm) | 29.31 |
| Package Width (mm) | 29.31 |
| Package Height (mm) | 3.68(Min) |
| Seated Plane Height (mm) | 4.37 |
| Pin Pitch (mm) | 1.27 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-018AF |
| Density | 128Kbit |
| Address Bus Width | 26bit |
| Maximum Access Time | 55ns |
| Timing Type | Asynchronous |
| Data Rate Architecture | SDR |
| Density in Bits | 131072bit |
| Maximum Operating Current | 250mA |
| Typical Operating Supply Voltage | 5V |
| Number of Bits per Word | 16bit |
| Number of Ports | 2 |
| Number of Words | 8K |
| Min Operating Supply Voltage | 4.5V |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | -55°C |
| Max Operating Temperature | 125°C |
Compliance
| Cage Code | SAN34 |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A001.a.2.c |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Renesas 7025L55JGB8 Datasheet
Download the complete datasheet for Renesas 7025L55JGB8 to view detailed technical specifications.
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