FIFO Mem Async Dual Depth/Width Uni-Dir 1K x 9 32-Pin PLCC T/R
Renesas 7202LA50JG8 technical specifications.
| Density | 9Kbit |
| Timing Type | Asynchronous |
| Configuration | Dual |
| Bus Directional | Uni-Directional |
| Maximum Operating Current | 80mA |
| Maximum Access Time | 50ns |
| Typical Operating Supply Voltage | 5V |
| Organization | 1Kx9 |
| Data Bus Width | 9bit |
| Expansion Support | Yes |
| Density in Bits | 9216bit |
| Min Operating Supply Voltage | 4.5V |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
| Pin Count | 32 |
| Package/Case | PLCC |
| Package Family Name | LCC |
| RoHS | Yes |
| RoHS Version | 2011/65/EU, 2015/863 |
No datasheet is available for this part.
