8634BK-01LFT

LVPECL differential clock driver with 5 outputs, featuring zero delay buffering. This surface-mount integrated circuit operates with differential input and output signals, supporting input logic levels including HCSL, LVDS, LVHSTL, LVPECL, and SSTL. It handles input and output frequencies up to 700 MHz, with a maximum cycle-to-cycle jitter of 25 ps and maximum output skew of 25 ps. The component is housed in a 32-pin VFQFN EP package measuring 5x5x0.95mm with a 0.5mm pin pitch.