9DBV0231AKILF

2-output, zero-delay clock buffer and driver featuring LP-HCSL differential signaling. This surface-mount integrated circuit operates with a 24-pin MLF EP package (4x4mm, 0.88mm height) and supports input frequencies from 30 MHz to 137.5 MHz. Key performance specifications include a maximum cycle-to-cycle jitter of 25 ps and maximum output skew of 50 ps. The device is designed for a -40°C to 85°C operating temperature range.