Zero delay buffer clock driver with 2 differential outputs. Features LP-HCSL output logic levels and HCSL input logic. Operates with input frequencies from 30 MHz to 137.5 MHz. Packaged in a 24-pin MLF EP (Micro Lead Frame, Exposed Pad) surface mount package with dimensions of 4x4x0.88 mm and a 0.5 mm pin pitch. Offers maximum cycle-to-cycle jitter of 25 ps and maximum output skew of 50 ps.
Renesas 9DBV0231AKLF technical specifications.
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