
Zero delay buffer clock driver featuring 8 differential LP-HCSL outputs from a single HCSL input. Operates across a 30 MHz to 137.5 MHz frequency range with a maximum cycle-to-cycle jitter of 25 ps and maximum output skew of 50 ps. This surface-mount component is housed in a 48-pin VFQFPN EP package (6x6x0.95mm) with a 0.4mm pin pitch, designed for optimal signal integrity. Suitable for applications requiring precise clock distribution within a 0°C to 70°C operating temperature range.
Renesas 9DBV0831AKLFT technical specifications.
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