**Clock Driver** featuring a zero-delay buffer with 6 differential outputs. Designed for SSTL-2 logic levels, this integrated circuit operates with a maximum frequency of 150 MHz and exhibits a typical output skew of 60 ps. The component is housed in a 48-pin SSOP (Shrink Small Outline Package) with gull-wing leads, suitable for surface mounting. Its lead-frame SMT basic package type conforms to JEDEC MO-118AA standards.
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Renesas 9P960AFLFT technical specifications.
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | SOP |
| Package/Case | SSOP |
| Package Description | Shrink Small Outline Package |
| Lead Shape | Gull-wing |
| Pin Count | 48 |
| PCB | 48 |
| Package Length (mm) | 15.88 |
| Package Width (mm) | 7.49 |
| Package Height (mm) | 2.29 |
| Seated Plane Height (mm) | 2.59 |
| Pin Pitch (mm) | 0.64 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MO-118AA |
| Type | Clock Driver |
| Number of Inputs | 1 |
| Number of Outputs | 6 |
| Input Signal Type | Differential |
| Output Signal Type | Differential |
| Output Logic Level | SSTL-2 |
| Minimum Output Frequency | 0MHz |
| Maximum Output Frequency | 150MHz |
| Maximum Output Skew | 60(Typ)ps |
| Spread Spectrum | No |
| Cage Code | SAN34 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
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