Dual D-type latch IC featuring high-level clock edge triggering and complementary outputs. This TTL technology component operates from a 5V supply, with a voltage range of 4.75V to 5.25V. It offers a propagation delay of 27ns at nominal supply and a maximum output low current of 8A. The device is housed in a 16-pin plastic dual in-line package (DIP) with a 2.54mm terminal pitch.
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Technical Specifications
Renesas HD74LS75P technical specifications.
General
| Clock Edge Trigger Type | HIGH LEVEL |
| Height - Seated (Max) | 5.06mm |
| JESD-30 Code | R-PDIP-T16 |
| JESD-609 Code | e0 |
| Length | 19.2mm |
| Logic IC Type | D LATCH |
| Max I(ol) | 8A |
| Max Operating Temperature | 75°C |
| Min Operating Temperature | -20°C |
| Number of Bits | 2 |
| Number of Functions | 2 |
| Output Polarity | Complementary |
| Package Body Material | Plastic |
| Package Code | DIP |
| Package Equivalence Code | DIP16,.3 |
| Package Shape | Rectangular |
| Package Style | IN-LINEMeter |
| Power Supplies | 5V |
| Power Supply Current-Max (ICC) | 12mA |
| Prop. Delay@Nom-Sup | 27ns |
| Propagation Delay (tpd) | 30ns |
| Qualification Status | Not Qualified |
| RoHS Compliant | No |
| Supply Voltage-Max (Vsup) | 5.25V |
| Supply Voltage-Min (Vsup) | 4.75V |
| Supply Voltage-Nom (Vsup) | 5V |
| Surface Mount | No |
| Technology | TTL |
| Temperature Grade | COMMERCIAL EXTENDED |
| Terminal Finish | Tin |
| Terminal Form | Through Hole |
| Terminal Pitch | 2.54mm |
| Terminal Position | DUAL |
| Width | 7.62mm |
Compliance
| RoHS | Not Compliant |
Datasheet
Renesas HD74LS75P Datasheet
Download the complete datasheet for Renesas HD74LS75P to view detailed technical specifications.
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