Synchronous SRAM chip with 36M-bit density, featuring a 2M x 18 configuration and QDR data rate architecture. Operates at a maximum clock rate of 303 MHz with a 1.8V supply voltage. Encased in a 165-pin FBGA package (17x15x1.08mm) for surface mounting. Supports a 20-bit address bus and offers dual ports. Extended operating temperature range from -40°C to 85°C.
PackageFBGA
MountingSurface Mount
Quick Jump:
Technical Specifications
Renesas R1Q2A3618BBG-33IS technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 165 |
| PCB | 165 |
| Package Length (mm) | 17 |
| Package Width (mm) | 15 |
| Package Height (mm) | 1.08 |
| Seated Plane Height (mm) | 1.4 |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 36Mbit |
| Address Bus Width | 20bit |
| Timing Type | Synchronous |
| Maximum Clock Rate | 303MHz |
| Data Rate Architecture | QDR |
| Density in Bits | 37748736bit |
| Maximum Operating Current | 650mA |
| Typical Operating Supply Voltage | 1.8V |
| Number of Bits per Word | 18bit |
| Number of Ports | 2 |
| Number of Words | 2M |
| Min Operating Supply Voltage | 1.7V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | SAN34 |
| EU RoHS | Yes |
| HTS Code | 8542320041 |
| Schedule B | 8542320040 |
| ECCN | 3A991.b.2.a |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Renesas R1Q2A3618BBG-33IS Datasheet
Download the complete datasheet for Renesas R1Q2A3618BBG-33IS to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.