GDDR3 SDRAM memory chip, 512Mbit density, organized as 16Mx32 with a 32-bit data bus width. Features a 1400 MHz maximum clock rate, 8 internal banks, and 2M words per bank. Operates at 1.8V typical supply voltage and is housed in a 136-pin FBGA package with a 0.8mm pin pitch. Surface mountable with a 0.26 ns maximum access time.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Samsung K4J52324KI-JC14 technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 136 |
| PCB | 136 |
| Package Length (mm) | 14 |
| Package Width (mm) | 10 |
| Seated Plane Height (mm) | 1.12 |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 512Mbit |
| Type | GDDR3 SDRAM |
| Organization | 16Mx32 |
| Data Bus Width | 32bit |
| Maximum Clock Rate | 1400MHz |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 2M |
| Maximum Access Time | 0.26ns |
| Density in Bits | 536870912bit |
| Address Bus Width | 15bit |
| Typical Operating Supply Voltage | 1.8V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Supply Voltage | 1.7V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
Compliance
| Cage Code | 1542F |
| HTS Code | 8542320028 |
| Schedule B | 8542320015 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
Datasheet
Samsung K4J52324KI-JC14 Datasheet
Download the complete datasheet for Samsung K4J52324KI-JC14 to view detailed technical specifications.
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