1Gbit DDR2 SDRAM memory chip, organized as 32Mx32, featuring a 32-bit data bus width and a maximum clock rate of 800 MHz. This surface-mount component utilizes a 128-pin FBGA package with dimensions of 13.5mm x 10.5mm x 0.8mm. Operating at a typical supply voltage of 1.8V, it offers 8 internal banks with 4M words per bank. The chip supports a minimum operating temperature of 0°C and a maximum of 95°C.
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| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 128 |
| PCB | 128 |
| Package Length (mm) | 13.5 |
| Package Width (mm) | 10.5 |
| Package Height (mm) | 0.8 |
| Seated Plane Height (mm) | 1.1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 1Gbit |
| Type | DDR2 SDRAM |
| Organization | 32Mx32 |
| Data Bus Width | 32bit |
| Maximum Clock Rate | 800MHz |
| Number of Internal Banks | 8 |
| Number of Words per Bank | 4M |
| Maximum Access Time | 0.4ns |
| Density in Bits | 1073741824bit |
| Address Bus Width | 15bit |
| Maximum Operating Current | 260mA |
| Typical Operating Supply Voltage | 1.8V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Supply Voltage | 1.7V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 95°C |
| Cage Code | 1542F |
| HTS Code | 8542320032 |
| Schedule B | 8542320015 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
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