DDR2 SDRAM memory chip, 512Mbit density, organized as 32Mx16 for a 16-bit data bus width. Features a maximum clock rate of 800 MHz, 4 internal banks, and 8M words per bank. Housed in an 84-pin FBGA package with a 0.8mm pin pitch, this surface-mount component operates at a typical supply voltage of 1.8V and has a maximum access time of 0.4 ns.
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| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 84 |
| PCB | 84 |
| Package Length (mm) | 12.5 |
| Package Width (mm) | 7.5 |
| Seated Plane Height (mm) | 1.1 |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 512Mbit |
| Type | DDR2 SDRAM |
| Organization | 32Mx16 |
| Data Bus Width | 16bit |
| Maximum Clock Rate | 800MHz |
| Number of Internal Banks | 4 |
| Number of Words per Bank | 8M |
| Maximum Access Time | 0.4ns |
| Density in Bits | 536870912bit |
| Address Bus Width | 15bit |
| Maximum Operating Current | 130mA |
| Typical Operating Supply Voltage | 1.8V |
| Max Operating Supply Voltage | 1.9V |
| Min Operating Supply Voltage | 1.7V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 95°C |
| Cage Code | 1542F |
| EU RoHS | Yes |
| HTS Code | 8542320028 |
| Schedule B | 8542320015 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
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